Agilent Technologies 8560E User Manual page 42

Quick Start Guide
Rear Panel Overview
To prevent damage to the instrument, be sure to set the voltage selector
CAUTION
to the appropriate value for your local line-voltage output. For more
information, refer to the "If You Have A Problem" chapter.
1. J4 VIDEO OUTPUT provides a detected video signal that is
2. J1 on 8560 E-series instruments (see 14 for information on J1 in
3. J5 EXT/GATE TRIG INPUT accepts a TTL signal as an external
For gated video triggering, the instrument sweep trigger depends upon
4. J6 BLKG/GATE OUTPUT provides either a blanking output or a
5. J2 GPIB is the General Purpose Interface Bus connector.
6. J3 OPTION MODULE allows connection of option modules such as
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proportional to the vertical deflection of the trace on the display. The
output range is 0 V to 1 V when terminated in 50 Ω. It can be used
when the display is in 10 dB/div or LINEAR mode. For resolution
bandwidth settings less than 300 Hz, a 4.8 kHz IF signal with a dc
offset is present at J4. The VIDEO OUTPUT connector is not
available with Option 327.
EC-series instruments) EARPHONE provides a 4 Ω impedance
earphone jack .
trigger, or as a trigger for gated video. The input signal range is 0 V
to 5 V (TTL). For external triggering, the instrument sweep triggers
on the rising or falling edge (as determined by
the signal (about +1.5 V).
the setting of
GATE CTL EDGE LVL
EDGE, either the positive or negative edge of the trigger input
signal initiates the gate delay. (Set
is set to level (LVL), either the TTL high level or
GATE CTL EDGE LVL
TTL low level opens the gate. (Set
control functions can be accessed by pressing
gate output.
The blanking output is a 0 V to 5 V (TTL) signal that is low (0 V)
during spectrum analyzer sweeps. The output is high (5 V) during
retrace and when the instrument is between bands in multiband
sweeps. Use this output for pen lift when plotting with nondigital
plotters. It is also useful for synchronizing instruments.
The gate output provides a TTL signal that indicates the status of
the gate when the gate is in edge trigger mode. A high TTL signal
indicates the gate is on; a low TTL signal indicates the gate is off.
The gate output is not active in level mode.
the 85620A mass memory module or the 85629B test and
adjustment module.
TRIG POL POS NEG
. If
GATE CTL EDGE LVL
EDGE POL POS NEG
.) The gate
LVL POL POS NEG
.
SWEEP
) of
is set to
.) If
Chapter 1