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System Interface Unit
IEXT—Instruction External Transfer Error Acknowledge
This bit is set if the cycle is terminated by an externally generated TEA signal when an
instruction fetch is initiated.
ITMT—Instruction Transfer Monitor Timeout
This bit is set if the cycle is terminated by a bus monitor timeout when an instruction fetch is
initiated.
IPB0–IPB3—Instruction Parity Error on Bytes 0–3
There are four parity error status bits for each byte lane. One of these is set for the byte that
had a parity error when an instruction was fetched. Parity check for a memory region that is
not controlled by the memory controller is enabled by the PNCS bit in the SIUMCR, as
shown in Section 12.12.1.1 SIU Module Configuration Register.
DEXT—Data External Transfer Error Acknowledge
This bit is set if the cycle is terminated by an externally generated TEA signal when a data
load or store is requested by an internal master.
DTMT—Data Transfer Monitor Timeout
This bit is set if the cycle is terminated by a bus monitor timeout when a data load or store
is requested by an internal master.
DPB0–DPB3—Data Parity Error On Bytes 0–3
There are four parity error status bits for each byte lane. One of these is set for the byte that
had a parity error when a data load was requested by an internal master. Parity check for a
memory region that is not controlled by the memory controller is enabled by the PNCS bit in
the SIUMCR, as shown in Section 12.12.1.1 SIU Module Configuration Register.
MOTOROLA
MPC823e REFERENCE MANUAL
12-37
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