Motorola MPC823e Reference Manual page 337

External Bus Interface
CLKOUT
BR0
BG0
BR1
BG1
BB
ADDR + ATTR
TS
TA
Figure 13-22. Bus Arbitration Timing Diagram
At system reset, the MPC823e can be configured to use the internal bus arbiter and it will
be parked on the bus. The priority of the external device relative to the internal MPC823e
bus masters is programmed in the SIUMCR, as described in Section 12.12.1.1 SIU Module
Configuration Register . If the external device requests the bus and the MPC823e does not
need it or the external device has priority over the current internal bus master, the MPC823e
grants the bus to the external device. Figure 13-23 illustrates the internal finite state
machine that implements the arbiter protocol.
13-30
MASTER 0 MASTER 0
NEGATES
"TURNS ON"
BB
AND
AND
DRIVES
"TURNS OFF"
SIGNALS
MPC823e REFERENCE MANUAL
MASTER 1
"TURNS ON"
AND
DRIVES
SIGNALS
MOTOROLA