Motorola MPC823e Reference Manual page 313

Microprocessor for mobile computing
Table of Contents

Advertisement

External Bus Interface
Table 13-1. Bus Interface Signals (Continued)
MNEMONIC
PINS
DP[0:3]
TRANSFER CYCLE TERMINATION
TA
TEA
BI
13-6
ACTIVE
I/O
4
High
I/O
Parity Bus —Each parity signal corresponds to each
one of the data bus lanes:
Data Bus Byte
D[0:7]
D[8:15]
D[16:23]
D[24:31]
O
Driven by the MPC823e when it owns the external bus
and has initiated a write transaction to a slave device.
Each parity signal has the parity value (even or odd)
of the corresponding data bus byte. For single beat
transactions, if external A[6:31] and TSIZ[0:1] do not
select the byte lanes for transfer, they will not have a
valid parity line.
I
Driven by the slave in a read transaction. Each parity
signal is sampled by the MPC823e and checked (if
enabled) against the expected value parity value
(even or odd) of the corresponding data bus byte. For
single beat transactions, if external A[6:31] and
TSIZ[0:1] do not select the byte lanes for transfer,
they will not be sampled by the MPC823e and its
parity signals will not be checked.
1
Low
I
Transfer Acknowledge —Driven by the slave device
the current transaction was addressed to. It indicates
that the slave has received the data on the write cycle
or returned the data on the read cycle. If the
transaction is a burst, TA must be asserted for each
one of the transaction beats.
O
Driven by the MPC823e when the slave device is
controlled by the on-chip memory controller.
1
Low
I
Transfer Error Acknowledge —Driven by the slave
device the current transaction was addressed to. It
indicates that an error condition has occurred during
the bus cycle.
O
Driven by the MPC823e when the internal bus monitor
detects an erroneous bus condition.
1
Low
I
Burst Inhibit —Driven by the slave device the current
transaction was addressed to. It indicates that the
current slave does not support burst mode.
O
Driven by the MPC823e when the slave device is
controlled by the on-chip memory controller.
MPC823e REFERENCE MANUAL
DESCRIPTION
Parity Line
DP0
DP1
DP2
DP3
MOTOROLA

Advertisement

Table of Contents
loading

Table of Contents