Motorola MPC823e Reference Manual page 361

ADDRESS[0:16], AT[0:2]
BASE REGISTER (BR)
BASE REGISTER (BR)
BASE REGISTER (BR)
BASE REGISTER (BR)
OPTION REGISTER (OR)
OPTION REGISTER (OR)
OPTION REGISTER (OR)
OPTION REGISTER (OR)
WRITE-PROTECT
LOGIC
MACHINE MODE REGISTER (M x MR)
MEMORY PERIODIC TIMER
MEMORY DISABLE TIMER
MEMORY COMMAND REGISTER (MCR)
MEMORY STATUS REGISTER (MSTAT)
MEMORY ADDRESS REGISTER (MAR)
MEMORY PERIODIC TIMER PRESCALE REGISTER (MPTPR)
Figure 15-1. Memory Controller Block Diagram (Single UPM)
MOTOROLA
BASE REGISTER (BR)
BASE REGISTER (BR)
BASE REGISTER (BR)
BASE REGISTER (BR)
OPTION REGISTER (OR)
OPTION REGISTER (OR)
OPTION REGISTER (OR)
OPTION REGISTER (OR)
WP
RD/WR
SCY[0:3]
WAIT STATE COUNTER
BURST, RD/WR
UPM ACCESS REQUEST
UPM ACCESS ACKNOWLEDGE
TURN ON DISABLE TIMER
ENABLE
UPM ACCESS REQUEST
(COMMAND)
UPM COMMAND
DONE
WP ERROR
PARITY ERROR
PARITY LOGIC
MPC823e REFERENCE MANUAL
MULTIPLEXER
INCREMENTOR
ATTRIBUTES
EXPIRED
GENERAL-PURPOSE
CHIP-SELECT
MACHINE
LOAD
UPM
USER-
ARBITER
PROGRAMMABLE
MACHINE
(A OR B)
MEMORY DATA REGISTER (MDR)
DP[0:3]
D[0:31]
Memory Controller
ADDRESS
LATCH
AND
NA AND
AMX FIELDS
CS[0:7]
WE[0:3]
OE
CS[0:7]
BS_x[0:3]
GPLx[0:5]
TA
DLT3 (INTERNAL)
UPWAITx
15-3