Table of Contents
Advertisement
SECTION 13
EXTERNAL BUS INTERFACE
The MPC823e bus is synchronous and burstable. Signals driven on this bus are required to
make the setup and hold time relative to the bus clock's rising edge. This bus has the ability
to support multiple masters. The MPC823e architecture supports byte, half-word, and word
operands allowing access to 8-,16-, and 32-bit data ports through the use of synchronous
cycles controlled by the transfer size output (TSIZx) signals. The slave access to 16- and
8-bit ports is controlled by the memory controller.
13.1 FEATURES
The following is a list of the bus interface's main features:
• 26-Bit Address Bus with Transfer Size Indication
• 32-Bit Data Bus
• TTL-Compatible Interface
• Compatible with PowerPC
• Interfaces to Slave Devices Easily
• Synchronous Bus Operation
• Data Parity Support
13.2 TRANSFER SIGNALS
The bus transfers information between the MPC823e and the external memory or peripheral
device. External devices can accept or provide 8,16, and 32 bits in parallel and must follow
the handshake protocol. The maximum number of bits accepted or provided during a bus
transfer is defined as the port width.
The MPC823e contains an address bus that specifies the transfer's address and a data bus
that transfers the data. Control signals indicate the beginning and type of the cycle, as well
as the address space and size of the transfer. The selected device then controls the length
of the cycle with the signal used to terminate the cycle. A strobe signal for the address bus
indicates the validity of the address and provides timing information for the data. The
MPC823e bus is synchronous, but the bus and control input signals must be timed to setup
and hold times relative to the rising edge of the clock. In this situation, bus cycles can be
completed in two clock cycles.
MOTOROLA
™
Architecture
MPC823e REFERENCE MANUAL
13-1
Advertisement
Table of Contents
