Pci Express* Design Guidelines; Pcie* General Introduction; Description; Supported Configuration Options For Pcie* Ports - Intel Quark SoC X1000 Design Manual

PCI Express* Design Guidelines—Intel
4.0

PCI Express* Design Guidelines

4.1

PCIe* General Introduction

4.1.1

Description

The Intel
root ports consist of one lane each configured as a 2x1 port. Each Root Port is PCIe*
2.0 compliant.
Table 13.

PCI Express* Root Ports Speed Support

PCIe* 1.0
PCIe* 2.0
The PCI Express* topology consists of a transmitter (TX) on one device connected by a
differential trace pair to a receiver (RX) on a second device. One of the devices may be
located on the baseboard or an add-in card.
4.1.2

Supported Configuration Options for PCIe* Ports

Table 14
Table 14.

PCIe* Root Ports 1 and2 Supported Configurations

Port 1
x1
4.1.3

PCI Express* Lane Polarity Inversion

The PCI Express* Base Spec requires polarity inversion to be supported independently
by all receivers across the Link - each differential pair within each Lane of the PCIe
Link handles its own polarity inversion. Polarity inversion is applied, as needed, during
the initial training sequence of the Lane. In other words, a Lane will still function
correctly even if a positive (TX+) signal from a transmitter is connected to the negative
(RX-) signal of the receiver. Polarity inversion eliminates the need to untangle a trace
route to reverse a signal polarity difference within a differential pair and no special
configuration settings are necessary in the SoC to enable it. It is important to note that
polarity inversion does not imply direction inversion or direction reversal, i.e., the TX
differential pair from one device must still connect to the RX differential pair on the
receiving device, per the PCIe Base Spec. Polarity Inversion is not the same as
Express* Port Lane
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
®
Quark™ SoC X1000 SoC provides two PCI Express* root ports. The PCIe*
Speed Bandwidth
2.5 GT/s
5 GT/s
describes the supported configurations for the PCIe ports.
Port 2
x1 2x1 mode, one lane to each port
Reversal". See
Each Direction (5 GT/s concurrent)
Each Direction (10 GT/s concurrent)
Notes
Figure 22 for an example.
Direction
"PCI
®
Intel Quark™ SoC X1000
PDG
41