Spi1_Miso - Intel Quark SoC X1000 Design Manual

Table 38.

SPI1_MISO

PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip /
Stripline / Dual Stripline)
Characteristic Impedance
(Single-ended)
Trace Width (w)
Trace Spacing(S2): Between
GPIO Signals
Trace Spacing(S3): Between
GPIO and other signals
Trace Segment Length
Data to Clock MB length matching rule
Number of vias
Rs
Reference Plane
1. This requirement relates to the platform routing and does not include the inter package routing.
Note: The guidelines regarding the routing of the GPIO based CS are TBD.
®
Intel Quark™ SoC X1000
PDG
70
®
Intel Quark™ SoC X1000—General Purpose SPI Interface Design Guidelines
Breakout
4 Layer
L
A
MS
4.2 mil
4.2 mil
4.2 mil
0.5"
1
4 Layer 4 Layer
L L
B C
MS MS
50 Ω +/- 15%
4.2 mil 4.2 mil
10 mil 10 mil
15 mil 15 mil
min = 0.1" min = 0.2"
max = 1.5" max = 0.8"
< 200mils
max 1
33ohm +/- 5%
Solid Ground Reference
Order Number: 330258-002US
4 Layer
L
D
MS
4.2 mil
10 mil
15 mil
0.25" max
June 2014