Design Checklist Items; Component Placement Review Checklist; General Routing Review Checklist - Intel Quark SoC X1000 Design Manual

Electromagnetic Interference—Intel
17.5

Design Checklist Items

This section provides a checklist that should be reviewed during the design process.
This checklist has been developed over time and experience to reduce the possibility of
unwanted emissions. The checklist is shown below. Not every suggestion is 100%
effective; attention to appropriate items can help reduce EMI. The design and layout of
the board must be reviewed by the appropriate EMC engineer assigned to the project
prior to committing to fabrication.
Table 56.

Component Placement Review Checklist

ITEM
NO.
169-1
169-2
169-3
169-4
Table 57.

General Routing Review Checklist

ITEM
NO.
170-1
170-2
170-3
170-4
170-5
170-6
170-7
170-8
170-9
170-10
170-11
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
Clock synthesizers, crystals, oscillators, microprocessor chips and other VLSI packages
have been placed in the center of the board, away from board edges, I/O connectors,
plane splits and other board mounted connectors to minimize radiation from the board.
Components using the same clock have been placed close to each other and the clock
source to minimize clock trace lengths.
Filter components have been placed adjacent to the pin they are filtering on
I/O connectors.
For non-differential clocks, provisions have been made for series termination of clock
traces at the source to minimize ringing.
Board stack-up designed to insure that all clocks and high-speed (> 1 MHz) traces are
routed in layers adjacent to power or ground planes.
Power planes have been recessed from the edge of the board.
Clock traces have been laid out first and kept as short as possible, consistent with the need
for matched clock trace lengths in the clock nets.
Clock and High-Speed traces do not change layers and do not cross breaks in power or
ground planes. Stitching capacitors must be used in areas were reference breaks are
unavoidable.
Clock and High-Speed traces have been kept away from board edges and traces leading to
connectors (internal or external connections).
Clock and High-Speed differential traces have been laid out to minimize length, consistent
with the need for matched trace lengths to minimize signal skew.
Do not route traces under clock generating circuits or other large high speed devices.
Ground pads with the same footprint as the part have been provided on the component
side of the board away from oscillators or clocks. These ground pads are tied to the ground
plane(s) of the board with multiple vias.
Provisions have been made for bonding the board ground system to the chassis at multiple
points. The best locations are at connectors and noise sources (clocks, microprocessors,
etc.).
Provisions have been made for grounding the heat plate or heat sink on the SOC(if applied)
to the board ground structure with a maximum spacing between ground points of 375 mils
 10 
(9.525 mm); .
Contiguous memory referencing topology must be maintained.
DESCRIPTION
DESCRIPTION
Y/N
Y/N
®
Intel Quark™ SoC X1000
PDG
125