Single-Ended Microstrip Diagram; Differential-Microstrip Diagram; Platform Stack-Up Parameter Values (Microstrip) - Intel Quark SoC X1000 Design Manual

• Reference plane stitching vias must be used in conjunction with high-speed signal
layer transitions that include a reference plane change. Refer to each signal group
section for more specification.
• The parameter values for internal and external traces are the final thickness and
width after the motherboard materials are laminated, conductors plated, and
etched. Intel uses these exact values to generate the associated electrical models
for simulation.
Figure 2.

Single-Ended Microstrip Diagram

Figure 3.

Differential-Microstrip Diagram


r 2

r 1
Power/GND Plane
Table 1. Platform Stack-up Parameter Values (Microstrip) (Sheet 1 of 2)
Microstrip Units
D1 mils
D2 mils

NA
r1

NA
r2
Trace Thickness
mils
(0.5 oz. Plated)
®
Intel Quark™ SoC X1000
PDG
18
Pair to pair pitch
- Manufac- - Design/
Min
turing Material
Value
Tolerance Tolerance
2.05 0.3
0.1 0.3
3.45 0.15
3.20 0.2
1.30 0.28
®
Intel Quark™ SoC X1000—Stack-Up and PCB Considerations
Microstrip
Pitch
W
+ Design/
Typical
Material
Value
Tolerance
0.4 2.75
0.25 0.65 0.25
0.3 3.9
0 3.40
0.32 1.90 0.32
D2
T
D1
+ Manufac-
turing
Tolerance
0.2 0.3
0.30
0.3 0.15
0 0.2
0.28
June 2014
Order Number: 330258-002US
Max
Value
3.25
1.20
4.35
3.60
2.50