7.3
SDIO Topology Guidelines
This section contains information and details for layout and routing guidelines for the
SDIO interfaces.
Figure 31.
SDIO Topology with Connector
CFIOHVTEW NO RCOMP
Table 29.
SDIO Layout Guideline
PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip / Stripline /
Dual Stripline)
Characteristic Impedance (Single-
ended)
Trace Width (w)
Trace Spacing(S2): Between SDIO
Signals
Trace Spacing(S3): Between SDIO
and other signals
Trace Segment Length
Note:
* Keep La + Lb as short as possible to give the best margin on the overshoot/undershoot violation.
Data to Clock MB length matching rule
Number of vias
Rs
Reference Plane
1. Relates to platform routing, inter-package routing not considered.
7.4
Terminating Unused SDIO Signals
If SDIO interface is not used, it should be terminated properly with external pull-up or
pull-down resistors.See
®
Intel
Quark™ SoC X1000
PDG
60
SoC
Breakout
L
A
Table 30
®
Intel
Quark™ SoC X1000—SDIO Interface Design Guidelines
Rs
L
B
Breakout
4 Layer
4 Layer
L
L
A
B
MS
MS
50 Ω +/-
50 Ω +/-
15%
10%
4.2 mil
4.2 mil
4.2 mil
10 mil
4.2 mil
10 mil
0.5" max
0.1" - 0.8"
1
regarding internal pull up/down.
E
L
L
S
D
C
D
4 Layer
4 Layer
L
C
MS
MS
50 Ω +/-
50 Ω +/-
10%
10%
4.2 mil
4.2 mil
10 mil
4.2 mil
10 mil
4.2 mil
0.1" - 3.0"
0.5" max
< 200mils
max 2
33 +/- 5%
Solid Ground Reference
June 2014
Order Number: 330258-002US
Connector
L
D