Terminology; Related Documents; Table 1. Terminology; Table 2. Related Documents - Intel Quark SoC X1000 User Manual

Introduction
1.1

Terminology

Table 1. Terminology
Term
ACPI Sx states
CLTAPC
Debug Software
JTAG
PIR
PRDY#
PREQ#
SoC
TAP
TDI
TDO
TDR
1.2

Related Documents

Table 2. Related Documents
®
Intel Quark SoC X1000 Datasheet
https://communities.intel.com/docs/DOC-21828
®
Intel Quark SoC X1000 Core Hardware Reference Manual
https://communities.intel.com/docs/DOC-21825
®
Intel Quark SoC X1000 Core Developer's Manual
https://communities.intel.com/docs/DOC-21826
Order Number: 329866-002US
Description
System sleep states as defined by the ACPI standard:
http://www.acpi.info/
Chip level TAP Controller. This is the top level standard compliant TAP
controller for the SoC.
Generic term for software that controls a hardware probe connected to
the JTAG pins.
"Joint Test Action Group" of the IEEE. This is now a generic term to
refer to the TAP and the pins used for communication with TAPs.
Probe Mode Instruction Register
Probe Mode Ready package pin (active low); this pin is used to signal
to Debug Software that the core has entered Probe Mode
Probe Mode Request package pin (active low); this pin may be used by
Debug Software to request that the core enter Probe Mode
System on chip
Test Access Port as defined by the IEEE 1149.1-1990 (including IEEE
1149.1a-1993), "IEEE Standard Test Access Port and Boundary-Scan
Architecture"
TAP Data In; the serial data input pin for the TAP chain
TAP Data Out; the serial data output pin for the TAP chain
TAP Data Register; a serial TAP data register selected by a TAP
instruction
Title and Location Document #
329676
329678
329679
5