Stack-Up And Pcb Considerations; Printed Circuit Board (Pcb) Considerations - Intel Quark SoC X1000 Design Manual

Stack-Up and PCB Considerations—Intel
2.0

Stack-Up and PCB Considerations

Note: Metric units are used in some sections in addition to the standard use of U.S.
customary system of units (USCS). If there is a discrepancy between the metric and
USCS units, assume the USCS unit is most accurate. The conversion factor used is 1
inch (1000 mils) = 25.4 mm.
2.1

Printed Circuit Board (PCB) Considerations

Several layer count configurations may be implemented on the platform, provided the
trace geometries of the individual microstrip and stripline routing layers fall within the
parameter value ranges and the impedance specifications are met. It is important to
note that variations in the stack-up of a motherboard, such as changes in the dielectric
height, trace widths, and spacing, can impact the impedance, loss, and jitter
characteristics of all the interfaces. Such changes may either be intentional or the
result of variations encountered during the PCB manufacturing process. In either case,
they must be properly considered when designing interconnects.
The following figures depict the set of geometry metrics associated with the external
(microstrip) routing and dual-stripline routing layers for both single-ended and
differential signals. The typical values and simulation sweep ranges for each parameter
are defined in the following tables. If motherboard parameters (including
manufacturing variances) fall outside of the boundaries shown, perform additional
simulations to ensure proper signal integrity and specification compliance.
• Design tolerances account for adjustments intentionally included in their design.
• Material tolerances account for any natural variation in the materials being used.
• Manufacturing tolerance considers variations that may occur during the
manufacturing process.
• Use the design tolerance to recenter stack-up impedance, but consider the
manufacturing tolerance impact when comparing the chosen stack-up to the given
recommendation.
The typical values, including the design and material tolerances, are centered around a
nominal single line impedance specification of 50  ±15% for microstrip. Many
interfaces specify a different nominal single-ended impedance. For more details on the
nominal trace width to hit those impedance targets, refer to the individual interface
section.
The following general stack-up recommendations should be followed:
• Microstrip layers are assumed to be built from ½ oz. foil, plated up nominally
another 1 oz., however, the trace thickness range defined allows for significant
process variance around this nominal.
• Based on Intel
1oz. copper.
• All high-speed signals should reference solid planes over the length of their routing
and should not cross plane splits. Ground referencing is preferred.
June 2014
Order Number: 330258-002US
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Quark™ SoC X1000
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Galileo layout layers 3/4 dual stripline assumed to be built from
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Intel Quark™ SoC X1000
PDG
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