Intel® Galileo Platform Power Delivery - Intel Quark SoC X1000 Design Manual

All internal supply voltages are brought out of the SoC package and looped back-in on
the platform (Refer to OVOUT_<name> in
to disconnect the internal LDO in certain cases and supply the rail with an external
voltage rail.
Note: Figure 47
®
Intel Quark™ SoC X1000 reference design schematics for the full implementation.
®
Figure 47. Intel Galileo Platform Power Delivery
V1P0_S5_PG
PLATFORM POWER 5V
The power-up sequence specified in
each step after the S5_PG signal asserts, the Intel
management block enables the subsequent power rails through a process of
handshaking. These enable signals are utilized on the platform to control the FET
switches which control the S3 and S0 power rails. Power good signals are needed by
®
the Intel
boundary crossing.
®
Intel Quark™ SoC X1000
PDG
98
Intel
Figure 47 illustrates the recommended platform power delivery.
is only a block diagram and should not be treated as schematic. Refer to the
Lvl shift
logic
PGOOD
EN1
VIN1 VOUT1
V3P3_S5
EN2
TPS652510
VOUT2
VIN2
V1P0_S5
EN3
VOUT3
VIN3
V1P5_S5
Quark™ SoC X1000 power management unit at each power domain
®
Quark™ SoC X1000—Platform Power Delivery Requirements
Figure 47). This allows the system designer
vout
vin V1P5_S0
TPS22920
on
SO_1V5_EN
V1P5_S5
RC-Delay S0_PGOOD
V3P3_S0
vout
vin
V3P3_S5
TPS22920
on S0_3V3_EN
V1P0_S0
vout
vin
TPS22920
V1P0_S5
on
SO_1V0_EN
RC-Delay PG_V1P0_S0
V3P3_S5 vout V3P3_S3
vin
TPS22920
on
S3_3V3_EN
V1P5_S3
vout
vin
V1P5_S5
TPS22920
on
S3_1V5_EN
S3_PGOOD
RC-Delay
Table 51 is described in detail with
®
Quark™ SoC X1000 internal power
OVOUT_1P05_S0 V1P05_S0_IVR
OVOUT_1P0_S3
V1P0_S3_IVR
VCC1P0_S3
V1P0_S5_IVR
OVOUT_1P0_S5
OVOUT_1P8_S0
V1P8_S0_IVR
OVOUT_1P8_S3
V1P8_S3_IVR
OVOUT_1P8_S5
V1P8_S5_IVR
TM
Intel® Quark SoC
X1000
Figure 48. At
June 2014
Order Number: 330258-002US