Pci Express* Expansion Card Routing Per To Connector - Intel Quark SoC X1000 Design Manual

1. Place the caps for P and N of a diff pair at exact same location
2. Symmetrically route the P and N from SOC to the Cap.
3. Symmetrically route the P and N from cap to the Connector
4. Stagger the caps of different differential pairs
Table 20.

PCI Express* Expansion Card Routing PER to Connector

Transmission Line Segment
PCB Routing Layer(s) Optional
Stackup Layer (Microstrip / Stripline/
Dual Stripline)
Characteristic Impedance
Trace Width (w)
Trace Spacing (S): Between P and N
within a diff pair
Trace Spacing(S1): Between PCIe*
PET/PER diff pairs
Trace Spacing(S2): Between PCIe* PET
diff pairs and PER diff pairs
Trace Spacing(S3): Between PCIe* diff
pairs and other signals
PET/ PER Trace Segment Length
Total Trace Length
Number of vias allowed
Length Matching Rules
Length Matching between P and N within a diff. pair
Length matching between Tx pairs of multiple lanes
Length matching between RX pairs of multiple lanes
General
Reference plane
®
Intel Quark™ SoC X1000
PDG
46
®
Intel Quark™ SoC X1000—PCI Express* Design Guidelines
P1/L0 L1
r r
4 Layer 4 Layer
MS MS
90 Ω diff 15% 90 Ω diff 15%
(MS) (MS)
4.0 mils 4.0 mils
4.0 mils 6.0 mils
12.0 mils 15.0 mils
12.0 mils 18.0 mils
12.0 mils 18.0 mils
min = 1500 mils
max = 400 mils max = 3000
mils
§ §
L2
r
4 Layer
MS
90 Ω diff 15%
(MS)
4.0 mils
6.0 mils
15.0 mils
15.0 mils
15.0 mils
max = 200 mils
RX Total Length = 3600 mils
2 via
+/- 10 mils
+/- 10 mils
+/- 10 mils
Continuous Ground Only
June 2014
Order Number: 330258-002US