Design-Pcb Type 3; Command Routing Guidelines And Settings For A Single Rank 4L Fly-By Design-Pcb Type; Ma/Bs/Cas/Ras/ We - Command Routing Topology For A Single Rank 4L Fly–By Design—Pcb Type 3 - Intel Quark SoC X1000 Design Manual

Table 9. Control - Routing Guidelines and Settings for a Single Rank 4L Fly-by Design—
PCB Type 3 (Sheet 2 of 2)
Parameter
Length matching
between point-to-point
CTRL signals and all
CTRL = (CLK/CLKB - 50 mils) ± 50 mils
the CLOCKs within a
Channel (including
pkg. length)
Number of vias max = 4 via
RON: 27 Ω
SoC BUffer Settings:
SR: 1.5 V/ns
RTT Value 36 Ω + 10%
Note: All length matching and total trace length rules are applicable for the SoC to DRAM
paths; for termination related segments i.e., TL8 and TL9 only the min and max trace
segment length rules apply.
Figure 19. MA/BS/CAS/RAS/ WE - Command Routing Topology for a Single Rank 4L Fly–
by Design—PCB Type 3
SoC
Tx
Table 10. Command Routing Guidelines and Settings for a Single Rank 4L Fly-by
Design—PCB Type 3 (Sheet 1 of 2)
Parameter
Transmission Line
Segment
Stackup Layer
(Microstrip / Stripline/
Dual Stripline)
Characteristic
Impedance (Command
Group)
Trace Width
Trace Spacing (S):
Within the signals in
the Command Group
®
Intel Quark™ SoC X1000
PDG
34
Package
Breakout Main
P1
TL1 TL2
via via
TL1 TL2
MS MS
40 Ω SE 10% (MS)
4.0 6.5
mils mils
min = min =
4.0 13.0
mils mils
®
Intel Quark™ SoC X1000—DDR3 Memory Design Guidelines
Routing Guideline / Setting
DRAM
Breakin
Breakout
Main Breakin Breakin
TL3 TL4 TL5 TL6
via
device-to-
-device
Routing Guideline / Setting
TL3 TL4 TL5 TL6
MS MS MS MS
6.5 4.0 4.0 6.5
mils mils mils mils
min = min = min = min =
6.5 4.0 4.0 6.5
mils mils mils mils
DRAM
VTT
Breakin
RTT
Breakin Breakout
Termination
TL7 TL8 TL9
via
TL7 TL8 TL9 TL10
MS MS MS MS
4.0 4.0 6.5 4.2
mils mils mils mils
min = min = min = min =
4.0 4.0 6.5 4.0
mils mils mils mils
June 2014
Order Number: 330258-002US