Probe Mode Exit; Reset Break; Tapstatus Register; Table 10. Tapstatus Data Register - Intel Quark SoC X1000 User Manual

configured to cause an entry to Probe Mode instead of allowing the exception handler
to run. See the
The PREQ pin must be pulsed to enter Probe Mode. The PROBEMODE TAP instruction
offers a TAP-based entry method as an alternative. To use the TAP-based Probe Mode
entry, write '1 to the PROBEMODE data register. The core will automatically redirect to
Probe Mode after a single step, hardware or software breakpoint. All entries to Probe
Mode are signaled to the Run Control Hardware via the PRDY# pin.
Note: The core requires that TCLK be running for it to latch PREQ# pin events for Probe
Mode entry.
5.3

Probe Mode Exit

Probe Mode exit is accomplished by writing a '0 to the PROBEMODE TAP instruction's
data register. Reset will also cause the core to leave Probe Mode.
5.4

Reset Break

In order to debug BIOS or firmware from the first instruction, the reset break
capability must be used. The Intel
two mechanisms. The first option depends on the PREQ# and PRDY# signals being
connected to the Hardware Probe. The second option is available for when the Debug
Tool is connected using only the JTAG pins.
Mechanisms for reset break:
1. Run Control hardware must monitor the target for RESET events so that it may
assert PREQ# prior to the rising edge of RESET# as sampled by the core.
2. Use the CLTAPC_CPU_VPREQ TDR detailed in
5.5

TAPSTATUS Register

The TAPSTATUS register is defined in the following table.

Table 10. TAPSTATUS Data Register

Bit Field
31:7
6
5
4
3
2
16
Probe Mode Control Register
®
Reserved
Shutdown Break Occurred. This bit is set to '1 when a shutdown break was the
cause for the break.
Shutdown Break is enabled. This is a copy of PMCR[1]
If '1, the core supports software breakpoints installed by debug software
Probe Mode Redirection. Holds value of PMCR[0].
Probe Mode In Progress. Held high while in Probe Mode and after register state
has been saved to shadow SRAM.
section below for full details.
Quark SoC X1000 Core supports reset break with
Section 2.3.4.
Description
Run Control
Order Number: 329866-002US