General Purpose Spi Interface Design Guidelines; General Introduction; Description; General Purpose Signal Descriptions - Intel Quark SoC X1000 Design Manual

General Purpose SPI Interface Design Guidelines—Intel
9.0

General Purpose SPI Interface Design Guidelines

9.1

General Introduction

9.1.1

Description

The two general-purpose SPI interfaces support various devices which use serial
protocols for transferring data such as sensors on the platform.
Each interface consists of 5 wires: a clock (CLK), two chip select's (CS0 & CS1) and 2
data lines (MOSI and MISO). The CS signals are generated from GPIO pins.
The general-purpose SPI is full-duplex synchronous serial interface. The SPI interface
operates in master mode only, and supports serial bit rate up to 25Mb/s. Serial data
formats may range from 4 to 32 bits in length.
9.2

General Purpose Signal Descriptions

9.2.1

Signal Groups

Table 34.

SPI Signals

Clock
Data
Chip Select
Chip Select
1. Though SPI0_SS_B is available as pins in order to support multiple SPI slaves they are not utilized.
2. Though SPI1_SS_B is available as pins in order to support multiple SPI slaves they are not utilized.
June 2014
Order Number: 330258-002US
Group
SPI0_SCK
SPI1_SCK
SPI0_MISO
SPI1_MISO
SPI0_MOSI
SPI1_MOSI
GPIO[0]
1
SPI 0
GPIO[1]
GPIO[2]
2
SPI 1
GPIO[3]
®
Quark™ SoC X1000
Signal Name Description
Clock signals
Master In Slave Out signals
Master Out Slave In signals
Chip select signals for SPI 0
Chip select signals for SPI 1
®
Intel Quark™ SoC X1000
PDG
67