Hardware Breakpoints; Software Breakpoints; Single Step; Redirections Into Probe Mode - Intel Quark SoC X1000 User Manual

Run Control
5.9

Hardware Breakpoints

1. Write the linear address to DR0-3.
2. Set DR6 and DR7 bits as needed.
3. Set bit 0 in PMCR to convert the #DB exception to a Probe Mode entry.
5.10

Software Breakpoints

To determine if an instance of the Intel
breakpoints, check bit 4 in the TAPSTATUS register. If the bit is '1, the core supports
software breakpoints.
Configure software breakpoints in the Core by replacing one byte of the original
instruction opcode(s) in memory with the value 0xF1 and setting PMCR[IR] to '1.
5.11

Single Step

1. Set EFLAGS[TF] to '1 and PMCR[IR] to '1.
2. Release from Probe Mode and wait for PRDY#.
On Probe Mode entry from SW break, debug software must decrement EIP by 1 before
replacing the 0xF1 with the real opcode byte.
5.12

Redirections into Probe Mode

5.12.1

Shutdown Break

The processor may be configured to enter Probe Mode when a SHUTDOWN event
occurs. This is enabled by setting bit 1 in the PMCR register to '1.
To determine if the cause for an asynchronous entry into Probe Mode was caused by a
shutdown break, bit 6 in the TAPSTATUS data register will be set to '1. PMCR bit 5
holds a copy of the enable bit in PMCR. This allows debug software to check if the
shutdown redirection is enabled without putting the core into Probe Mode.
Order Number: 329866-002US
®
Quark SoC X1000 Core supports software
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