Additional Guidelines; S0_3V3_En Usage Model; S0_1V5_En Usage Model; S0_1V0_En Usage Model - Intel Quark SoC X1000 Design Manual

15.3

Additional Guidelines

15.3.1

S0_3V3_EN Usage Model

S0_3V3_EN is used primary to control platform V3P3 VR so that it will enter a more
power efficient mode outside S0. It may also be used to power off all non-critical
components outside the S0 state. This signal should be connected to a VR controller to
enter low power mode.
15.3.2

S0_1V5_EN Usage Model

S0_1V5_EN is used to power off all non-critical 1.5V components when not in the S0
state.
15.3.3

S0_1V0_EN Usage Model

S0_1V0_EN is used to power off the 1.0v domain and other non-critical components
outside the S0 state.
Note: For the S0 state to be in a stable power state all S0 rail enables must be active, in
addition to the S3 rail enables.
15.3.4

S3_3V3_EN Usage Model

S3_3V3_EN is used primary to control platform V3P3 VR so that it will enter a more
power efficient mode in S4 or S5 state.
15.3.5

S3_1V5_EN Usage Model

S3_1V5_EN is used to power off all non-critical 1.5V components when in S4 or S5
state.
Note: For the S3 state to be in a stable power state all S3 rail enables must be active.
15.3.6

PWRBTN# Usage Model

The Power Button signal (PWRBTN#) on the Intel
connected directly to the power button on the system's front panel header. When
system power button is pressed, PWRBTN# should be pulled low. The SoC has 2.5ms or
more of internal debounce logic on this pin, external debouncing circuit is not required.
Alternatively where a front panel button is not required the PWRBTN can be tied low
which results in the SoC auto booting once power is applied in S5.
15.3.7

RSTBTN# Usage Model

The Reset Button signal (RSTBTN#) on SoC can be connected directly to the reset
button on the system's front panel header. When system reset button is pressed,
RSTBTN# should be pulled low. The SoC has 2.6 ms of internal debounce logic on this
pin, external debouncing circuit is not required. This button has several functions
dependent on system state. If in S3 sleep a RSTBTN press will result in the SOC waking
from S3 to S0. If in S0 a RSTBTN press will result in the SOC performing a WARM reset.
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Intel Quark™ SoC X1000
PDG
102
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Intel Quark™ SoC X1000—Platform Reset Considerations
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Quark™ SoC X1000 can be
June 2014
Order Number: 330258-002US