Reference Planes; Backward And Forward Coupling Coefficient Calculation; Electrical Limits Of Lh Material Properties - Intel Quark SoC X1000 Design Manual

performed on several high-speed buses and validation platforms were built to help
identify electrical limits of LH materials that will help ensure 1) adequate bus
performance and 2) interchangeability between FR4 and LH material. The layout
constraints listed in this document have been designed to function with both standard
FR4 and LH materials if the electrical properties of the LH materials fall within the
envelope defined by
Table 2.

Electrical Limits of LH Material Properties

Permittivity (Er)
Loss Tangent (tan
Moisture Impact on Loss (tan
Note: Approximate limits of desired electrical performance of LH dielectric materials; RC =% Resin Content,
RH = Relative Humidity; 1080 stackups have between ~ 60-65% resin content depending on the layer
thickness; Limits established using buses implemented on 1080 material. 2116 (RC=45%) and
RC=50% limits extrapolated from the 1080 data points using the volume ratio of resin to glass and
average values of resin density, glass density, glass permittivity, glass tan and glass weight basis.
Although the limits listed in
FR4, simulated and measured data indicate that they are sufficient to ensure proper
functionality of the buses listed in this design guide. Since the volume of LH materials
on the market is small compared to FR4, the performance envelope was made as large
as practical to maximize the number of LH materials that comply without significantly
sacrificing signal integrity.
However, if the limits are adhered to, then the risk of signal integrity problems due to
the LH material is greatly reduced. Intel bases signal integrity analysis and validation
on these ranges.
Designers should also ensure the LH dielectric materials chosen meet all applicable
thermal, mechanical and UL flammability requirements.
2.3

Reference Planes

• Reference all signal routing layers to a solid ground plane that is continuous over
the length of the interconnect. Specific requirements may be defined within the
interface design guideline chapters.
• Using a power layer as a reference plane is allowed if the power layer is low noise
and there is proper decoupling stitching at reference planes transitions to
guarantee high frequency return path continuity. However, this should only be
considered as the secondary reference plane on internal layers where a solid
continuous ground reference is already present. Even in this case the power plane
must be low noise due to the possibility of noise being coupled into the associated
signal planes.
• Route noisy power planes, such as VBAT, on the same layers as signals to minimize
fringe coupling by proper spacing separation.
2.4

Backward and Forward Coupling Coefficient Calculation

Some designs require a stack-up build that is outside of the ranges provided. In this
case, compare the routing electrical characteristics versus the Intel recommendation.
®
Intel Quark™ SoC X1000
PDG
20
Table 2.
Parameter Approximate LH Electrical Limits

)

)
Table 2
Table 2
®
Intel Quark™ SoC X1000—Stack-Up and PCB Considerations
<4.2 (1080, RC~61%)
<4.3 (RC~50%)
<4.5 (2116, RC~45%)
<0.018 (1080, RC~61%)
<0.014 (1080, RC~50%)
<0.013 (2116, RC~45%)
<0.024(1080, RC~61%)
<0.019(RC=50%)
<0.017 (2116, RC~45%)
are generally lower performance than standard
does not guarantee equal performance to FR4.
Environmental Condition
Any environmental conditions
50% RH & 75oF
95% RH & 95oF
June 2014
Order Number: 330258-002US