Pci Express* Port Lane Reversal; Pch Pcie* Disabling And Termination Guidelines; Length Matching Guidelines; Impedance Compensation And Voltage Reference - Intel Quark SoC X1000 Design Manual

Figure 22.

Polarity Inversion on a TX to RX Interconnect

4.1.4

PCI Express* Port Lane Reversal

As each PCIe port link is a single lane, Lane Reversal is not supported in SoC.
4.1.5

PCH PCIe* Disabling and Termination Guidelines

• If some of the PCI Express ports are not implemented on the platform:
— PETp/n [x] and PERp/n [x] signals may be left unconnected, where 'x' is the
port number left no connect.
• If no PCI Express ports are implemented on the platform:
— PETp/n [1:0] and PERp/n [1:0] may be left unconnected.
• Pull-up Wake# to VCC_SUS 3.3 via a 10-k? resistor.
Note: If used, check with latest version of the Intel® Quark SoC x1000 Datasheet for
maximum leakage specification on PCIE_WAKE# pin while selecting a pull up resistor in
order to ensure Vih at SOC pin is satisfied.
4.1.6

Length Matching Guidelines

The key about differential signal length-matching is that the differential signal pair
components (i.e., the p and n signals) must be kept in-phase during the entire length
of the traces (from beginning to end). Most board designers try to keep the overall
trace length of the individual p and n differential signals matched to within 10 mils
(Table 19) of each other. However, this is not sufficient - or necessarily correct. It is
important to do length-matching on a per-segment basis, in order to ensure the
differential signals are kept in-phase, which gives optimal differential impedance and
Common Mode rejection. Further length-matching information can be found in
Appendix A, "General Differential Signals Design
4.1.7

Impedance Compensation and Voltage Reference

The compensation input is used by the circuitry to determine, check and adjust the
system buffer output strength and characteristic impedance over temperature, process
and voltage variations. This is done by comparing its buffer impedance against a
standard reference resistor, RCOMP.
The RCOMP signals should be referenced to VSS. Noisy or switching references should
be avoided. As board space allows, it is recommended to add a VSS shield at least 4
mils wide placed between PCIE_IRCOMP/PCIE_RBIAS and adjacent I/O. No shield is
needed between PCIE_RBIAS and PCIE_IRCOMP.
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Quark™ SoC X1000—PCI Express* Design Guidelines
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June 2014
Order Number: 330258-002US