Usb 2.0 Mini Pcie Topology; Usb 2.0 External Routing Guidelines Mini Pcie - Intel Quark SoC X1000 Design Manual

Universal Serial Bus 2.0 Design Guidelines—Intel
Figure 27.

USB 2.0 Mini PCIe Topology

Table 23.

USB 2.0 External Routing Guidelines Mini PCIe*

PCB Routing Layer(s) Optional
Transmission Line Segment
Routing Layer (Microstrip / Stripline /
Dual Stripline)
Characteristic Impedance (Differential)
Trace Width (w)
Trace Spacing (S1): Between P and N of
clock pair
Trace Spacing (S2): Between USB2
different pairs
Trace Spacing (S3): Between USB2 pairs
and other signals
Trace Segment Length
Note: Can support up to 2" on the Mini PCIe Card
Length Matching Rules
Length Matching between P and N within a diff. pair
General
Number of vias
Routing Symmetry
Layer Assignment
Reference plane
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
SoC
Breakout
L
A1
TX
L
A1'
L L
B C
L L
B' C'
Breakout
4 Layer 4 Layer
L L
A B
MS MS
90 Ω +/- 90 Ω +/-
10% 10%
4.0 mil 4.0 mil
4.0 mil 6.0 mil
6.0 mil 15 mil
6.0 mil 25 mil
0.5" max 0.1" - 2.0"
+/- 5 mil
max 3 vias
Symmetrical routing of P and N of a diff
pair including vias
See recommendations above
Ground Only
Mini
L
D
PCIe*
L Conn
D'
4 Layer 4 Layer
L L
C D
MS MS
90 Ω +/- 90 Ω +/-
10% 10%
4.0 mil 4.0 mil
6.0 mil 6.0 mil
15 mil 15 mil
25 mil 25 mil
0.2" max 0.5" max
®
Intel Quark™ SoC X1000
PDG
51