Platform Reset Considerations; Platform Reset General Introduction; Description; Signal Description - Intel Quark SoC X1000 Design Manual

Platform Reset Considerations—Intel
15.0

Platform Reset Considerations

15.1

Platform Reset General Introduction

15.1.1

Description

Platform reset signals is a group of reset signals that control power on sequence, power
management, and provide proper reset to all components on the platform. This chapter
provides detailed guideline on how to generate and use platform reset signal to ensure
functionality of the platform.
15.2

Signal Description

15.2.1

Signal Groups

Signals listed in
Table 52.

Platform Reset Signals

Group
Power
Management
Power
Management
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
Table 52 are identified as platform reset signals from the SoC.
Signal Name
S5_PGOOD S5_PG
S3_PGOOD S3_PG
PG_V1P0_S0 S0_1P0_PG
S0_PGOOD S0_PG
DRAMPWROK ODRAM_PWROK
S0_1V0_EN S0_1V0_EN
S0_1V5_EN S0_1V5_EN
S0_3V3_EN S0_3V3_EN
S3_1V5_EN S3_1V5_EN
S3_3V3_EN S3_3V3_EN
EC_PWRBTN_N PWR_BTN
RESET_N RESET_BTN
Pin Description
Platform S5 power is okay
Platform S3 power is okay
Platform S0 power for 1.0v is okay
Platform S0 power for 1.5 is okay
DRAM Power OK
Voltage enable for S0 v1.0 rail
Voltage enable for S0 v1.5 rail
Voltage enable for S0 v3.3 rail
Voltage enable for S3 v1.5 rail
Voltage enable for S3 v3.3 rail
Power Button
Reset Button
®
Intel Quark™ SoC X1000
PDG
101