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CHAPTER 21 MULTI-PULSE GENERATOR
21.4 Interrupts
21.4
Interrupts
The multi-pulse generator can generate an interrupt request due to the
following sources:
• Write timing output is generated by the data write control unit
• Any valid position detection input is detected
• Comparison match between CPD[2:0] in the 16-bit MPG input control register
(upper) (IPCUR:CPD[2:0]) and RDA[2:0] in the 16-bit MPG output data register
(upper) (OPDUR:RDA[2:0])
• Compare clear is generated by the 16-bit timer
• DTTI is changed to the "L" level
■ Multi-pulse Generator Interrupts
There are five interrupts generated from the multi-pulse generator as follows:
• Write timing interrupt
• Compare clear interrupt
• Position detect interrupt
• Compare match interrupt
• DTTI interrupt
The write timing interrupt is multiplexed with the compare clear interrupt, and the position
detect interrupt with the compare match interrupt.
● Write timing interrupt
If the WTIE bit in the 16-bit MPG output control register (upper) (OPCUR) is set to "1", this
write timing interrupt is generated when the write timing is generated by the data write control
circuit to make data transfer from one of 12 pairs of 16-bit MPG output data buffer register
(upper/lower) (OPDBRHB and OPDBRLB - OPDBRH0 and OPDBRL0) to the 16-bit MPG
output data register (upper/lower) (OPDUR/OPDLR).
When this interrupt is generated, the write timing interrupt flag bit in the 16-bit output control
register (upper) (OPCUR:WTIF) is set to "1".
● Compare clear interrupt
If the ICRE bit in the 16-bit MPG timer control status register (TCSR) is set to "1", this
compare clear interrupt is generated when the compare value and the 16-bit timer value match.
When this interrupt is generated, the compare clear interrupt flag bit in the 16-bit MPG timer
control register (TCSR:ICLR) is set to "1".
● Position detect timing interrupt
If the PDIE bit in the 16-bit MPG output control register (lower) (OPCLR) is set to "1", this
position detect interrupt is generated when the write timing is output by the position detect
circuit to make data transfer from one of 12 pairs of 16-bit MPG output data buffer register
(upper/lower) (OPDBRHB and OPDBRLB - OPDBRH0 and OPDBRL0) to the 16-bit MPG
output data register (upper/lower) (OPDUR/OPDLR). This write timing output can be
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