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MB95630H Series
22.5
Interrupts
The UART/SIO has six interrupt-related bits: receive error flag bits (PER, OVE,
FER), receive data register full flag bit (RDRF), transmit data register empty flag
bit (TDRE), and transmission completion flag bit (TCPL).
■ Interrupts of UART/SIO
Table 22.5-1 lists the UART/SIO interrupt control bits and interrupt sources.
Table 22.5-1 UART/SIO Interrupt Control Bits and Interrupt Sources
Item
Interrupt request
SSRn:TDRE
flag bit
Interrupt request
SMC2n:TEIE
enable bit
Transmit data
Interrupt source
register empty
■ Transmit Interrupt
When transmit data is written to the UART/SIO serial output data register (TDRn), the data is
transferred to the transmission shift register. When the next piece of data can be written, the
TDRE bit is set to "1". At this time, an interrupt request to the interrupt controller occurs when
transmit data register empty interrupt enable bit has been enabled (SMC2n:TEIE = 1).
The TCPL bit is set to "1" upon completion of transmission of all pieces of transmit data. At
this time, an interrupt request to the interrupt controller occurs when transmission completion
interrupt enable bit has been enabled (SMC2n:TCIE = 1).
■ Receive Interrupt
If the data is input successfully up to the stop bit, the RDRF bit is set to "1". If an overrun
error, a parity error, or a framing error occurs, the corresponding error flag bit (PER, OVE, or
FER) is set to "1".
These bits are set when a stop bit is detected. If receive interrupt enable bit has been enabled
(SMC2n:RIE = 1), an interrupt request to the interrupt controller will be generated.
MN702-00009-1v0-E
SSRn:TCPL
SSRn:RDRF
SMC2n:TCIE
SMC2n:RIE
Transmission
Receive data full
completion
FUJITSU SEMICONDUCTOR LIMITED
Description
SSRn:PER
SSRn:OVE
SMC2n:RIE
SMC2n:RIE
Parity error
Overrun error
CHAPTER 22 UART/SIO
22.5 Interrupts
SSRn:FER
SMC2n:RIE
Framing error
461
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