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CHAPTER 14 LIN-UART
14.2 Configuration
● Receive control circuit
This block consists of a receive bit counter, a start bit detection circuit, and a receive parity
counter. The receive bit counter counts the receive data bits and sets a flag in the LIN-UART
receive data register when the reception of one data is completed according to the specified
data length. If the receive interrupt has been enabled, a receive interrupt request is made. The
start bit detection circuit detects a start bit in a serial input signal. When a start bit is detected,
the circuit sends a signal to the reload counter in synchronization with the start bit falling edge.
The receive parity counter calculates the parity of the received data.
● Receive shift register
The circuit captures received data from the SIN pin while performing bit shifting of received
data. The receive shift register transfers received data to the RDR register.
● LIN-UART receive data register (RDR)
This register retains the received data. Serial input data is converted and stored in the LIN-
UART receive data register.
● Transmit control circuit
This block consists of a transmit bit counter, a transmit start circuit, and a transmit parity
counter. The transmit bit counter counts the transmit data bits and sets a flag in the transmit
data register when the transmission of one data is completed according to the specified data
length. If the transmit interrupt has been enabled, a transmit interrupt request is made. The
transmit start circuit starts transmission when data is written to the TDR. The transmit parity
counter generates a parity bit for data to be transmitted if the data has a parity.
● Transmit shift register
Data written to the LIN-UART transmit data register (TDR) is transferred to the transmit shift
register, and then the transmit shift register outputs the data to the SOT pin while performing
bit shifting of the data.
● LIN-UART transmit data register (TDR)
This register sets the transmit data. Data written to this register is converted to serial data and
then output.
● Error detection circuit
This circuit detects errors occurring at the end of reception. If an error occurs, a corresponding
error flag is set.
● Oversampling circuit
In asynchronous mode, the oversampling circuit oversamples received data for five times to
determine the received value by majority of sampling values. The circuit stops operating in
synchronous mode.
● Interrupt generation circuit
This circuit controls all interrupt sources. An interrupt is generated immediately provided that
the corresponding interrupt enable bit has been set.
202
FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
MN702-00009-1v0-E
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