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22.6.2
Operations in Operation Mode 1 ................................................................................ 470
22.7
Registers ......................................................................................................................... 476
22.7.1
UART/SIO Serial Mode Control Register 1 (SMC1n) ................................................. 477
22.7.2
UART/SIO Serial Mode Control Register 2 (SMC2n) ................................................. 479
22.7.3
UART/SIO Serial Status and Data Register (SSRn) .................................................. 481
22.7.4
UART/SIO Serial Input Data Register (RDRn) ........................................................... 483
22.7.5
UART/SIO Serial Output Data Register (TDRn) ......................................................... 484
CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR ................ 485
23.1
Overview .......................................................................................................................... 486
23.2
Channel ........................................................................................................................... 487
23.3
Operations ....................................................................................................................... 488
23.4
Registers ......................................................................................................................... 489
23.4.1
23.4.2
2
C BUS INTERFACE .................................................................. 493
24.1
Overview .......................................................................................................................... 494
24.2
Configuration ................................................................................................................... 495
24.3
Channel ........................................................................................................................... 498
24.4
Pins .................................................................................................................................. 499
24.5
Interrupts ......................................................................................................................... 500
24.6
Operations and Setting Procedure Example ................................................................... 502
2
24.6.1
l
C Bus Interface ........................................................................................................ 503
24.6.2
Function to Wake up the MCU from Standby Mode ................................................... 511
24.7
Registers ......................................................................................................................... 513
2
24.7.1
C Bus Control Register 0 (IBCR0n) ......................................................................... 514
2
24.7.2
I
C Bus Control Register 1 (IBCR1n) ......................................................................... 517
2
24.7.3
C Bus Status Register (IBSRn) ................................................................................ 521
2
24.7.4
C Data Register (IDDRn) ......................................................................................... 524
2
24.7.5
C Address Register (IAARn) .................................................................................... 525
2
24.7.6
C Clock Control Register (ICCRn) ........................................................................... 526
24.8
CHAPTER 25 DUAL OPERATION FLASH MEMORY ....................................... 531
25.1
Overview .......................................................................................................................... 532
25.2
Sector/Bank Configuration ............................................................................................... 534
25.3
Invoking Flash Memory Automatic Algorithm .................................................................. 535
25.4
Checking Automatic Algorithm Execution Status ............................................................ 537
25.4.1
Data Polling Flag (DQ7) ............................................................................................. 539
25.4.2
Toggle Bit Flag (DQ6) ................................................................................................. 541
25.4.3
Execution Timeout Flag (DQ5) ................................................................................... 542
25.4.4
Sector Erase Timer Flag (DQ3) .................................................................................. 543
25.4.5
Toggle Bit2 Flag (DQ2) ............................................................................................... 544
25.5
Programming/Erasing Flash Memory .............................................................................. 545
25.5.1
Placing Flash Memory in Read/Reset State ............................................................... 546
25.5.2
Programming Data to Flash Memory .......................................................................... 547
25.5.3
Erasing All Data from Flash Memory (Chip Erase) ..................................................... 549
25.5.4
Erasing Specific Data from Flash Memory (Sector Erase) ......................................... 550
2
C Bus Interface .................................................................................... 528
xi
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