Clock Monitoring Data Register (Cmdr) - Fujitsu MB95630H Series Hardware Manual

MB95630H Series
17.4.1

Clock Monitoring Data Register (CMDR)

The clock monitoring data register (CMDR) is used to read the count value after
the clock supervisor counter stops. The software can check whether the
external clock frequency is correct or not according to the content of this
register.
■ Register Configuration
bit 7
Field CMDR7
Attribute R
Initial value 0
■ Register Functions
The clock monitoring data register (CMDR) is used to read the counter value after the clock supervisor
counter stops.
• The counter value can be read from the clock monitoring data register (CMDR). The software can check
whether the external clock frequency is correct or not according to the counter value read and the time-base
timer interval selected.
[bit7:0] CMDR[7:0]: Clock monitoring data bits
These bits indicate the clock supervisor counter value after the counter stops.
These bits are cleared if one of the following events occurs:
• Reset
• The CMCEN bit in the CMCR register (CMCR:CMCEN) is modified from "0" to "1" by the software.
• The CMCEN bit is modified from "1" to "0" by the software while the counter is running.
• After the external clock stops, the falling edge of the selected time-base timer clock is detected twice. (See
Figure 17.5-2.)
Note:
The value of this register is "0b00000000" as long as the counter is operating
(CMCR:CMCEN = 1).
MN702-00009-1v0-E
6 5
CMDR6 CMDR5
R R
0 0
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 17 CLOCK SUPERVISOR COUNTER
4 3
CMDR4 CMDR3
R R
0 0
17.4 Registers
2 1
CMDR2 CMDR1
R R
0 0
0
CMDR0
R
0
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