Fujitsu MB95630H Series Hardware Manual page 105

8-bit microcontroller new 8fx
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MB95630H Series
Operation at reset
If the CPU is reset, all bits in the DDRx register are initialized to "0" and port input is enabled.
As for a pin shared with analog input, its port input is disabled because the AIDRH/AIDRL
register is initialized to "0".
Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to "1" and the
device transits to stop mode or watch mode, the pin is compulsorily made to enter the high
impedance state regardless of the DDRx register value. The input of that pin is locked at "L"
level and blocked in order to prevent leaks due to input open. However, if the interrupt input
is enabled for the external interrupt, the input is enabled and not blocked.
• If the pin state setting bit is "0", the state of the port I/O or that of the peripheral function
I/O remains unchanged and the output level is maintained.
Operation as an analog input pin
• Set the bit in the DDRx register corresponding to the analog input pin to "0" and the bit
corresponding to that pin in the AIDRH/AIDRL register to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions. In addition, set the corresponding bit in the PULx register to "0".
Operation as an external interrupt input pin
• Set the bit in the DDRx register corresponding to the external interrupt input pin to "0".
• For a pin shared with other peripheral functions, disable the output of such peripheral
functions.
• The pin value is always input to the external interrupt circuit. When using a pin for a
function other than the interrupt, disable the external interrupt function corresponding to
that pin.
Operation of the pull-up register
Setting the bit in the PULx register to "1" makes the pull-up resistor be internally connected to
the pin. When the pin output is "L" level, the pull-up resistor is disconnected regardless of the
value of the PULx register.
MN702-00009-1v0-E
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 6 I/O PORT
6.2 Configuration and Operations
85

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