Uart/Sio Serial Mode Control Register 2 (Smc2N) - Fujitsu MB95630H Series Hardware Manual

MB95630H Series
22.7.2

UART/SIO Serial Mode Control Register 2 (SMC2n)

The UART/SIO serial mode control register 2 (SMC2n) controls the UART/SIO
operation mode. The register enables or disables serial clock output, serial
data output, transmission/reception, and interrupts, and clears the receive
error flag.
■ Register Configuration
bit 7
Field SCKE
Attribute R/W
Initial value 0
■ Register Functions
[bit7] SCKE: Serial clock output enable bit
This bit controls the input/output of the serial clock pin (UCKn) in clock synchronous mode (SIO).
bit7
Writing "0"
Writing "1"
Note: With the clock select bit (SMC1n:CKS) already set to "1", no internal clock signal is output even
when this bit set to "1".
In clock asynchronous mode (UART) (SMC1n:MD = 0), when this bit is set to "0", the output from
the UCKn bit will always be "H".
[bit6] TXOE: Serial data output enable bite bit
This bit controls the output of the serial data pin (UOn).
bit6
Writing "0"
Writing "1"
[bit5] RERC: Receive error flag clear bit
This bit clears the receive error flags.
The read value of this bit is always "1".
bit5
Writing "0"
Writing "1"
MN702-00009-1v0-E
6 5
TXOE RERC
R/W R/W
0 1
Disables the serial clock, and makes the UCKn pin function as a general purpose I/O port.
Enables the serial clock, and makes the UCKn pin function as a serial clock output pin.
Disables serial data output, and makes the UOn pin function as a general purpose I/O port.
Enables serial data output, and makes the UOn pin function as a serial data output pin.
Clears the receive error flags (PER, OVE and FER) in the SSRn register.
Has no effect on operation.
FUJITSU SEMICONDUCTOR LIMITED
4 3
RXE TXE
R/W R/W
0 0
Details
Details
Details
CHAPTER 22 UART/SIO
22.7 Registers
2 1
RIE TCIE
R/W R/W
0 0
0
TEIE
R/W
0
479