Table of Contents
Advertisement
CHAPTER 22 UART/SIO
22.7 Registers
[bit2] RDRF: Receive data register full flag bit
This bit indicates the state of the UART/SIO serial input data register (RDRn).
When receive data is loaded to the RDRn register, this bit is set to "1".
When data in the RDRn register is read, this bit is cleared to "0".
bit2
Reading "0"
Reading "1"
[bit1] TCPL: Transmission completion flag bit
This bit indicates the data transmission state.
When serial transmission is completed, this bit is set to "1". However, when the UART/SIO serial output data
register (TDRn) contains data to be transmitted successively, this bit is not set to "1" even after one time of
transmission is completed.
Writing "0" to this bit clears it.
When transmission completion setting this bit to "1" and writing "0" to this bit to clear it occur
simultaneously, the former one is given priority.
Writing "1" to this bit has no effect on operation.
bit1
Reading "0"
Reading "1"
Writing "0"
Writing "1"
[bit0] TDRE: Transmit data register empty flag bit
This bit indicates the state of the UART/SIO serial output data register (TDRn).
When transmit data is written to the TDRn register, this bit is set to "0".
When transmit data is loaded to the shift register for the transmission and data transmission starts, this bit is
set to "1".
bit0
Reading "0"
Reading "1"
482
Indicates that there is no receive data in the RDRn register.
Indicates that there is receive data in the RDRn register.
Indicates that data transmission has not been completed.
Indicates that data transmission has been completed.
Clears this bit.
Has no effect on operation.
Indicates that there is transmit data in the TDRn register.
Indicates that there is no transmit data in the TDRn register.
FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
Details
Details
Details
MN702-00009-1v0-E
Advertisement
Table of Contents
