Fujitsu MB95630H Series Hardware Manual page 468

8-bit microcontroller new 8fx

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Table of Contents

CHAPTER 21 MULTI-PULSE GENERATOR

21.6 Registers

[bit4] ICRE: Compare clear interrupt enable bit

This bit enables or disables the compare clear interrupt.

When this bit is set to "1", and the compare clear interrupt request flag bit (ICLR) is also set to "1", a

compare clear interrupt is generated.

[bit3] TMEN: Timer enable bit

This bit enables or disables the counting operation of the 16-bit timer.

Note: When the counting operation of the 16-bit timer is disabled, the output compare operation is also

[bit2:0] CLK[2:0]: Clock frequency select bits

These bits select the count clock of the 16-bit timer.

Writing "000"

Writing "001"

Writing "010"

Writing "011"

Writing "100"

Writing "101"

Writing "110"

Writing "111"

Note: Since the count clock is changed immediately after these bits are updated, it is recommend to modify

these bits while the 16-bit timer is in stop state.

Disables the compare clear interrupt.

Enables the compare clear interrupt.

Disables the counting operation of the 16-bit timer.

Enables the counting operation of the 16-bit timer.

MCLK = 16 MHz MCLK = 8 MHz

FUJITSU SEMICONDUCTOR LIMITED

(MCLK: machine clock)

MB95630H Series

MCLK = 4 MHz

MCLK = 1 MHz

MN702-00009-1v0-E