Fujitsu MB95630H Series Hardware Manual page 124

CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER
8.3 Operations and Setting Procedure
Example
Note:
The watchdog timer is also cleared when the timer selected as the count clock (time-
base timer or watch prescaler) is cleared. For this reason, the watchdog timer cannot
function if the software is set to repeatedly clear the timer selected as the count clock
of the watchdog timer at the interval time selected for the watchdog timer.
●
Interval time
The interval time varies depending on the timing of clearing the watchdog timer. Figure 8.3-1
shows the correlation between the timing of clearing the watchdog timer and the interval time
when the time-base timer output F
(main clock = 4 MHz).
Figure 8.3-1 Clearing Timing and Interval Time of Watchdog Timer
Minimum time
Time-base timer
count clock output
Watchdog 1-bit
counter
Watchdog reset
Maximum time
Time-base timer
count clock output
Watchdog 1-bit
counter
Watchdog reset
●
Operation in subclock mode
When a watchdog reset is generated in subclock mode, the timer starts operating in main clock
mode after the oscillation stabilization wait time has elapsed. The reset signal is output during
this oscillation stabilization wait time.
104
21
/2
CH
524 ms
Watchdog cleared
Watchdog cleared
FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
(F : main clock) is selected as the count clock
CH
Overflow
1.05 s
Overflow
MN702-00009-1v0-E