8-Bit Prescaler + 8-Bit Ppg Mode - Fujitsu MB95630H Series Hardware Manual

MB95630H Series
18.6.2

8-bit Prescaler + 8-bit PPG Mode

In this mode, the rising and falling edge detection pulses from the PPG timer
n1 output can be used as the count clock of the PPG timer n0 downcounter to
allow variable-cycle 8-bit PPG output from PPG timer n0.
■ Setting 8-bit Prescaler + 8-bit PPG Mode
The 8/16-bit PPG requires the register settings shown in Figure 18.6-3 to operate in 8-bit
prescaler + 8-bit PPG mode.
Figure 18.6-3 Setting 8-bit Prescaler + 8-bit PPG Mode
PCn1
PCn0
PPSn1
PPSn0
PDSn1
PDSn0
PPGS
REVC
: Used bit
0 : Set to "0"
1 : Set to "1"
× : Setting nullified
* : The bit status varies depending of the number of channels implemented
■ Operation of 8-bit Prescaler + 8-bit PPG Mode
• This mode is selected by setting the operation mode select bits (MD[1:0]) in the 8/16-bit
PPG timer n0 control register (PCn0) to "0b01". This allows PPG timer n1 to be used as an
8-bit prescaler and PPG timer n0 to be used as an 8-bit PPG.
• When the PPG timer n1 (ch. n) downcounter operation enable bit (PEN01) is set to "1", the
8-bit prescaler (PPG timer n1) loads the value in the 8/16-bit PPG timer n1 cycle setup
buffer register (PPSn1) and starts down-count operation. When the value of the
downcounter matches the value in the 8/16-bit PPG timer n1 duty setup buffer register
(PDSn1), the PPGn1 output is set to "H" synchronizing with the count clock. After "H"
which is the value of duty setting is output, the PPGn1 output is set to "L". If the output
level reverse signal (REV01) is "0", the polarity remains the same. If it is "1", the polarity is
MN702-00009-1v0-E
bit7 bit6 bit5
- - PIE1
MD1 MD0 PIE0
0 1
PH7 PH6 PH5
Set PPG output cycle for PPG timer n1
PL7 PL6 PL5
Set PPG output cycle for PPG timer n0
DH7 DH6 DH5
Set PPG output duty for PPG timer n1
DL7 DL6 DL5
Set PPG output duty for PPG timer n0
- - PEN21 PEN20 PEN11 PEN10 PEN01 PEN00
* * *
- - REV21 REV20 REV11 REV10 REV01 REV00
* * *
FUJITSU SEMICONDUCTOR LIMITED
18.6 Operations and Setting Procedure Example
bit4 bit3 bit2
PUF1 POEN1 CKS12 CKS11 CKS10
PUF0 POEN0 CKS02 CKS01 CKS00
×
PH4 PH3 PH2
PL4 PL3 PL2
DH4 DH3 DH2
DL4 DL3 DL2
* * *
* * *
CHAPTER 18 8/16-BIT PPG
bit1 bit0
× ×
PH1 PH0
PL1 PL0
DH1 DH0
DL1 DL0
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