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MB95630H Series
■ Signal Flow Diagram for Reload Timer or Position Detection by Setting
OPS[2:0] = 0b100 or 0b101
Figure 21.5-10 Signal Flow Diagram for Reload Timer or Position Detect (OPS[2:0] = 0b100 or
16-BIT RELOAD TIMER
OPDBRH0/OPDBRL0
WRITE SIGNAL
SNI2 to
Pin
SNI0
At this setting the write signal is generated by the compare match or effective edge input of the
position detection or after an underflow occurs in the 16-bit reload timer. The compare match
is triggered by any effective edge change in SNI2 to SNI0 pins.
■ OPDUR and OPDLR Write Timing Diagram
(OPS[2:0] = 0b001, 0b010, 0b011, 0b100, 0b101, 0b110, or 0b111)
Figure 21.5-11 OPDUR and OPDLR Write Timing Diagram
(OPS[2:0] = 0b001, 0b010, 0b011, 0b100, 0b101, 0b110, or 0b111)
OPS[2:0]
BNKF,
0b0001
RDA[2:0]
(OPDUR)
OPDBRL1[0]
OPDBRL4[0]
OPDBRL7[0]
WTO
OP00
MN702-00009-1v0-E
TIN
TIN0O
TOUT
WTIN0
ODBR0W
POSITION
WTIN1
DETECTION
0b001, 0b010, 0b011, 0b100, 0b101, 0b110, or 0b111
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 21 MULTI-PULSE GENERATOR
0b101)
DATA WRITE CONTROL UNIT
0b0100
21.5 Operations
Pin
TI1
TIN0
WRITE
WTO
TIMING
OUTPUT
0b0111
399
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