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MB95630H Series
● Notes on selecting the transfer complete timing
•
The transfer complete timing select bit (IBCR0n:INTS) is valid only during data reception
(IBSRn:TRX = 0 and IBSRn:FBT = 0).
•
In an operation other than data reception (IBSRn:TRX = 1 or IBSRn:FBT = 1), the transfer
completion interrupt (IBCR1n:INT) is always generated in the ninth SCLn cycle.
•
If the data acknowledge depends on the content of the received data (such as packet error
checking used by the SM bus), control the data acknowledge by setting the data
acknowledge enable bit (IBCR1n:DACKE) after writing "1" to the IBCR0n:INTS bit (for
example, using a previous transfer completion interrupt) to read latest received data.
•
The latest data acknowledge (IBSRn:LRB) can be read after the acknowledge is received
(IBSRn:LRB must be read at a transfer completion interrupt in the ninth SCLn cycle.)
Therefore, if an acknowledge is read with the IBCR0n:INTS bit set to "1", write "0" to the
INTS bit at a transfer completion interrupt generated in the eighth SCLn cycle so that
another transfer completion interrupt is to be generated in the ninth SCLn cycle.
● Notes on using the MCU standby mode wakeup function
•
Write "1" to the IBCR0n:WUE bit right before the MCU enters stop mode or watch mode.
To ensure that the I
mode or watch mode, clear (write "0" to) this bit as soon as possible.
•
When a wakeup interrupt request is generated, the MCU wakes up after the oscillation
stabilization wait time elapses. In order to prevent data loss from occurring immediately
after the MCU wakes up, after 100 µs (assuming that the minimum oscillation stabilization
wait time is 100 µs) elapses since a wakeup caused by the start of I
detection of the falling edge of SDAn), the SCLn must rise in the first cycle and the first bit
must be received as data.
•
In standby mode of the MCU, the status flags, state machine, and I
function keep their states existing before the MCU entered standby mode. To prevent a
hang-up of the entire I
MCU enter standby mode.
•
The wakeup function does not support the transition of the MCU to stop mode or watch
mode with the BB bit set to "1". When the MCU enters stop mode or watch mode with the
BB bit set to "1", a bus error occurs upon detection of a START condition.
•
To ensure that the I
IBCR0n:WUE to "0" after the MCU wakes up from stop mode or watch mode, regardless
of whether the MCU has been woken up by to the I
function of another resource (such as an external interrupt).
MN702-00009-1v0-E
2
C operation can restart immediately after the MCU wakes up from stop
2
C bus system, ensure that IBSRn:BB is set to "0" before making the
2
C bus interface operation correctly executes its operation, always clear
FUJITSU SEMICONDUCTOR LIMITED
2
CHAPTER 24 I
C BUS INTERFACE
2
24.8 Notes on Using I
2
C transmission (upon
2
C bus output for the I
2
C wakeup function or the wakeup
C Bus Interface
2
C
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