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MB95630H Series
■ Stop Condition
The master can release the bus and end communications by generating a stop condition.
Changing the SDAn line from "L" to "H" while SCLn is "H" generates a stop condition. This
signals to the other devices on the bus that the master has finished communications (referred to
below as "bus free"). However, the master can continue to generate start conditions without
generating a stop condition. This is called a repeated start condition.
Writing "0" to the IBCR1n:MSS bit during an interrupt while in master mode (IBCR1n:MSS =
1, IBSRn:BB = 1, IBCR1n:INT = 1, and IBCR0n:ALF = 0) generates a stop condition and
changes to slave mode. In other cases, writing "0" to the IBCR1n:MSS bit is ignored.
■ Arbitration
The interface circuit is a true multi-master bus able to connect multiple master devices.
Arbitration occurs when another master within the system simultaneously transfers data during
a master transfer.
Arbitration occurs on the SDAn line while the SCLn line is at the "H" level. When the send
data is "1" and the data on the SDAn line is "L" at the master, this is treated as arbitration lost.
In this case, data output is halted and IBCR0n:ALF is set to "1". If this occurs, an interrupt is
generated if arbitration lost interrupts have been enabled (IBCR0n:ALE = 1). If IBCR0n:ALF
is set to "1", the module sets IBCR1n:MSS = 0 and IBSRn:TRX = 0, clears TRX, and goes to
slave receive mode.
If IBCR0n:ALF is set to "1" when IBSRn:BB = 0, IBCR0n:ALF is cleared only by writing "0".
If IBCR0n:ALF is set to "1" when IBSRn:BB = 1, IBCR0n:ALF is cleared only by clearing
IBCR1n:INT to "0".
● Conditions for generating an arbitration lost interrupt when IBSRn:BB = 0
When a start condition is generated by the program (by setting the IBCR1n:MSS bit to "1") at
the timing shown in Figure 24.6-3 or Figure 24.6-4, interrupt generation (IBCR1n:INT = 1) is
prohibited by arbitration lost detection (IBCR0n:ALF = 1).
•
Conditions (1) in which no interrupt is generated due to arbitration lost
If the program triggers a start condition (by setting the IBCR1n:MSS bit to "1") when no start
condition has been detected (IBSRn:BB = 0) and the SDAn and SCLn line pins are at the "L"
level.
MN702-00009-1v0-E
24.6 Operations and Setting Procedure Example
FUJITSU SEMICONDUCTOR LIMITED
2
CHAPTER 24 I
C BUS INTERFACE
507
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