Fujitsu MB95630H Series Hardware Manual page 428

8-bit microcontroller new 8fx
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CHAPTER 21 MULTI-PULSE GENERATOR
21.5 Operations
The comparisons between the SNI2 pin and the RDA2 bit, the SNI1 pin and the RDA1 bit, the
SNI0 pin and the RDA0 bit are done for each position detection.
The OPTx output waveform is updated according to the effective edge input to pin SNIx as
shown in Figure 21.5-17. The data of the 16-bit MPG output data buffer register (upper/lower)
(OPDBRHx/OPDBRLx) specified by the BNKF bit and the RDA[2:0] bits is transferred to the
16-bit MPG output data register (upper/lower) (OPDUR/OPDLR), and the output data is
renewed automatically when pins SNI2 to SNI0 are compared with the value of the RDA[2:0]
bits and matches.
The reload timer can be used in this operation mode.
■ Timing Generated by Position Detection (OPS[2:0] = 0b010)
Figure 21.5-17 Timing Generated by Position Detection (OPS[2:0] = 0b010)
SNI2
SNI1
SNI0
RDA[2:0]
0b100
(OPDUR)
WTIN1
WTO
OP0[1:0]
0b00
(OPDLR)
PPG
OPT0
408
0b110
0b101
0b01
0b11
FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
0b011
0b001
0b00
0b10
MN702-00009-1v0-E
0b11

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