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MB95630H Series
● Continuous clock supply
When the CCO bit in the ESCR register is "1", the serial clock output from the SCK pin is
continuously supplied on the serial clock transmission side. In this case, add the start bit and
the stop bit to the data format (SSM = 1) in order to identify the beginning and end of the data
frame. Figure 14.6-6 shows the operation of continuous clock supply (operating mode 2).
Figure 14.6-6 Continuous Clock Supply (Operating Mode 2)
Transmit/receive clock
(SCES = 0, CCO = 1):
Transmit/receive clock
(SCES = 1, CCO = 1):
Data stream (SSM = 1)
(No parity, 1 stop bit)
● Error detection
When the start bit and the stop bit are disabled (ECCR:SSM = 0), only overrun errors are to be
detected.
● Communication settings for synchronous mode
To perform communications in synchronous mode, the following settings are required.
• LIN-UART baud rate generator registers 1, 0 (BGR1, BGR0)
Set the dedicated baud rate reload counter to a required value.
• LIN-UART serial mode register (SMR)
MD[1:0]: "0b10" (Operating mode 2)
SCKE : "1"– Uses the dedicated baud rate reload counter
SOE
• LIN-UART serial control register (SCR)
RXE, TXE: Set either bit to "1".
AD : Since the address/data format selection function is not used, the value of this bit has
CL : Since the bit length is automatically set to 8 bits, the value of this bit has no effect
CRE : "1": Clears the error flag in the SSR register.
- For SSM = 0:
PEN, P, SBL: Since neither the parity bit nor the stop bit is used, the values of these three
bits have no effect on operation.
- For SSM = 1:
PEN : "1": Adds/detects parity bit, "0": Not use parity bit
P
SBL : "1": Stop bit length 2,
MN702-00009-1v0-E
: "0"– Inputs an external clock
: "1"– Enables transmission/reception
: "0"– Enables only reception
no effect on operation.
on operation.
: "1": Even parity,
FUJITSU SEMICONDUCTOR LIMITED
14.6 Operations of LIN-UART and LIN-UART
ST
Data frame
"0": Odd parity
"0": Stop bit length 1
CHAPTER 14 LIN-UART
Setting Procedure Example
SP
229
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