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CHAPTER 21 MULTI-PULSE GENERATOR
21.5 Operations
■ DTTI Circuit Timing Diagram (D[1:0] = 0b00)
Figure 21.5-26 DTTI Circuit Timing Diagram (D[1:0] = 0b00)
MCLK
DTTI
DTIE
NRSL
DTIF*
DTISP
DTTI
DTIE
NRSL
DTIF*
DTISP
* DTIF is cleared by writing "0" to it.
Note:
In the worst case the time from DTTI being recognized (after noise cancellation) to DTISP
in effect takes 2 cycles, in best case it takes 1 cycle.
418
4 Cycles
FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
MN702-00009-1v0-E
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