Interrupt Level Setting Registers (Ilr0 To Ilr5) - Fujitsu MB95630H Series Hardware Manual

MB95630H Series
5.1.1

Interrupt Level Setting Registers (ILR0 to ILR5)

The interrupt level setting registers (ILR0 to ILR5) contain 24 pairs of 2-bit data
assigned to the interrupt requests of different peripheral functions. Each pair
of bits (interrupt level setting bits) is used to set the interrupt level of an
interrupt request.
■ Register Configuration
ILR0
bit 7
Field L03[1:0]
Attribute R/W
Initial value 1
ILR1
bit 7
Field L07[1:0]
Attribute R/W
Initial value 1
ILR2
bit 7
Field L11[1:0]
Attribute R/W
Initial value 1
ILR3
bit 7
Field L15[1:0]
Attribute R/W
Initial value 1
ILR4
bit 7
Field L19[1:0]
Attribute R/W
Initial value 1
ILR5
bit 7
Field L23[1:0]
Attribute R/W
Initial value 1
The interrupt level setting registers assign a pair of bits to every interrupt request. The values
of interrupt level setting bits in these registers represent the priority of an interrupt request
(interrupt level: 0 to 3) in interrupt processing.
MN702-00009-1v0-E
6 5
L02[1:0]
R/W R/W
1 1
6 5
L06[1:0]
R/W R/W
1 1
6 5
L10[1:0]
R/W R/W
1 1
6 5
L14[1:0]
R/W R/W
1 1
6 5
L18[1:0]
R/W R/W
1 1
6 5
L22[1:0]
R/W R/W
1 1
FUJITSU SEMICONDUCTOR LIMITED
4 3
L01[1:0]
R/W R/W
1 1
4 3
L05[1:0]
R/W R/W
1 1
4 3
L09[1:0]
R/W R/W
1 1
4 3
L13[1:0]
R/W R/W
1 1
4 3
L17[1:0]
R/W R/W
1 1
4 3
L21[1:0]
R/W R/W
1 1
CHAPTER 5 INTERRUPTS
5.1 Interrupts
2 1
L00[1:0]
R/W R/W
1 1
2 1
L04[1:0]
R/W R/W
1 1
2 1
L08[1:0]
R/W R/W
1 1
2 1
L12[1:0]
R/W R/W
1 1
2 1
L16[1:0]
R/W R/W
1 1
2 1
L20[1:0]
R/W R/W
1 1
0
R/W
1
0
R/W
1
0
R/W
1
0
R/W
1
0
R/W
1
0
R/W
1
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