Fujitsu MB95630H Series Hardware Manual page 276

8-bit microcontroller new 8fx

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CHAPTER 14 LIN-UART

14.7 Registers

[bit4] SCDE: Serial clock delay enable bit

In operating mode 2 in which the serial clock transmission side is selected, if the SCDE bit is set to "1", a

delayed serial clock as shown in Figure 14.6-5 is output. The function of outputting delayed serial clock can

be used in the Serial Peripheral Interface (SPI).

This bit is fixed at "0" in operating mode 0/1/3.

[bit3] SSM: Start/stop bits mode enable bit

In operating mode 2, if this bit is set to "1", the start/stop bits are added to the synchronous data format.

In operating mode 0/1/3, this bit is fixed at "0".

[bit2] Reserved bit

Always set this bit to "0".

[bit1] RBI: Receive bus idle detection flag bit

If the SIN pin is at "H" level and no reception is executed, this bit is "1". Do not use this bit when SSM = 0 in

operating mode 2.

[bit0] TBI: Transmit bus idle detection flag bit

If there is no transmission on the SOT pin, this bit is "1". Do not use this bit when SSM = 0 in operating

Disables serial clock delay.

Enables serial clock delay.

Disables the start/stop bits.

Enables the start/stop bits.

Indicates that reception is in progress.

Indicates that there is no reception operation.

Indicates that transmission is in progress.

Indicates that there is no transmission operation.

FUJITSU SEMICONDUCTOR LIMITED

Details (only for operating mode 2)

MB95630H Series

MN702-00009-1v0-E