Table of Contents
Advertisement
CONTENTS
MEMORY ACCESS MODE .............................................................. 1
1.1
Memory Access Mode ......................................................................................................... 2
CPU .................................................................................................. 3
2.1
Dedicated Registers ............................................................................................................ 4
2.1.1
Register Bank Pointer (RP) ............................................................................................ 6
2.1.2
Direct Bank Pointer (DP) ................................................................................................ 7
2.1.3
Condition Code Register (CCR) ..................................................................................... 9
2.2
General-purpose Register ................................................................................................. 11
2.3
Placement of 16-bit Data in Memory ................................................................................. 13
CLOCK CONTROLLER ................................................................. 15
3.1
Overview ............................................................................................................................ 16
3.2
Oscillation Stabilization Wait Time .................................................................................... 24
3.3
Registers ........................................................................................................................... 27
3.3.1
System Clock Control Register (SYCC) ....................................................................... 28
3.3.2
PLL Control Register (PLLC) ........................................................................................ 29
3.3.3
Oscillation Stabilization Wait Time Setting Register (WATR) ....................................... 30
3.3.4
Standby Control Register (STBC) ................................................................................ 32
3.3.5
System Clock Control Register 2 (SYCC2) .................................................................. 34
3.3.6
Standby Control Register 2 (STBC2) ........................................................................... 36
3.4
Clock Modes ...................................................................................................................... 37
3.5
Operations in Low Power Consumption Mode (Standby Mode) ........................................ 41
3.5.1
Notes on Using Standby Mode ..................................................................................... 42
3.5.2
Sleep Mode .................................................................................................................. 48
3.5.3
Stop Mode .................................................................................................................... 49
3.5.4
Time-base Timer Mode ................................................................................................ 51
3.5.5
Watch Mode ................................................................................................................. 53
3.6
Clock Oscillator Circuit ...................................................................................................... 54
3.7
Overview of Prescaler ....................................................................................................... 55
3.8
Configuration of Prescaler ................................................................................................. 56
3.9
Operation of Prescaler ....................................................................................................... 57
3.10
Notes on Using Prescaler .................................................................................................. 59
RESET ............................................................................................ 61
4.1
Reset Operation ................................................................................................................ 62
4.2
Register ............................................................................................................................. 66
4.2.1
Reset Source Register (RSRR) .................................................................................... 67
4.3
Notes on Using Reset ........................................................................................................ 70
INTERRUPTS ................................................................................. 71
5.1
Interrupts ........................................................................................................................... 72
5.1.1
Interrupt Level Setting Registers (ILR0 to ILR5) ........................................................... 73
5.1.2
Interrupt Processing ..................................................................................................... 75
v
Advertisement
Table of Contents
