Fujitsu MB95630H Series Hardware Manual page 43

MB95630H Series
Table 3.1-4 Combinations of Standby Mode and Clock Mode and Internal Operating States (2)
Time-base timer
Function
Main clock
mode
Main clock Operating
Main CR clock/
*2
Main CR PLL
Stopped
clock
Subclock
Operating
Sub-CR clock
Operating
CPU Stopped
Flash memory
Value held
RAM Value held
I/O ports Output held / Hi-Z
Time-base timer Operating
Watch prescaler
Operating
External interrupt Operating
Hardware
Operating
watchdog timer
Software watchdog
Stopped
timer
Low-voltage
Operating
detection reset
Other peripheral
Stopped
functions
*1: The main clock runs when the main clock oscillation enable bit in the system clock control register 2
(SYCC2:MOSCE) is set to "1".
*2: The main CR clock or the main CR PLL clock runs when main CR clock oscillation enable bit in the system
clock control register 2 (SYCC2:MCRE) is set to "1".
*3: The module runs when the subclock oscillation enable bit in the system clock control register 2
(SYCC2:SOSCE) is set to "1".
*4: The module runs when the sub-CR clock oscillation enable bit in the system clock control register 2
(SYCC2:SCRE) is set to "1".
*5: The hardware watchdog timer stops when the hardware watchdog timer is disabled by the non-volatile
register (NVR) interface.
*6: The state of the Flash memory in a standby mode can be selected from two options, normal state and low-
power state, by the deep standby mode control bit in the standby control register 2 (STBC2:DSTBYX).
MN702-00009-1v0-E
Watch
Main CR
clock mode/ Subclock
Main CR PLL mode
clock mode
*1
Stopped
Stopped
Operating Stopped
*3
Operating
*4 *4
Operating
Stopped
*6
Value held
Value held
Output held/Hi-Z
Stopped
*3, *4
Operating
Operating
*5
Operating
Stopped
Operating
Stopped
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 3 CLOCK CONTROLLER
Sub-CR Main clock clock mode/
clock mode mode Main CR PLL
*3
Operating Operating
Operating
Operating
*6
Operating
*5
3.1 Overview
Stop
Main CR
Subclock
mode clock mode
clock mode
Stopped
Stopped
*3
Stopped
*4
Stopped
Stopped
*6
Value held
Value held
Output held/Hi-Z
Stopped
*3, 4
Stopped
Operating
*5
Operating
Stopped
Operating
Stopped
Sub-CR
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