I 2 C Data Register (Iddrn) - Fujitsu MB95630H Series Hardware Manual

2
CHAPTER 24 I C BUS INTERFACE
24.7 Registers
2
24.7.4 I C Data Register (IDDRn)
2
The I C data register (IDDRn) sets the data or address to be transmitted, and
holds the data or address received.
■ Register Configuration
bit 7
Field D7
Attribute R/W
Initial value 0
■ Register Functions
In transmit mode, each bit of the data or address value written to the register is shifted to the
SDAn line, starting with the MSB. The write side of this register is double-buffered, where if
the bus is in use (IBSRn:BB = 1), the write data is loaded to the 8-bit shift register either when
the current data transfer completion interrupt is cleared (writing "0" to the IBCR1n:INT bit) or
when a repeated start condition is generated (writing "1" to the IBCR1n:SCC bit). Each bit of
the shift register data is output (shifted) to the SDAn line.
Note that writing to this register has no effect on the current data transfer. In slave mode,
however, data is transferred to the shift register after the address is determined.
The received data or address can be read from this register at the transfer completion interrupt
(IBCR1n:INT = 1). However, since the serial transfer register is directly read from when the
received data or address is read, the receive data is valid only when the INT bit is "1".
524
6 5
D6 D5
R/W R/W
0 0
FUJITSU SEMICONDUCTOR LIMITED
4 3
D4 D3
R/W R/W
0 0
MB95630H Series
2 1
D2 D1
R/W R/W
0 0
MN702-00009-1v0-E
0
D0
R/W
0