System Configuration Register (Sysc) - Fujitsu MB95630H Series Hardware Manual

CHAPTER 28 SYSTEM CONFIGURATION CONTROLLER
28.2 Register
28.2.1

System Configuration Register (SYSC)

This section describes the system configuration register.
■ Register Configuration
bit 7
Field PGSEL
Attribute R/W
Initial value 1
■ Register Functions
[bit7] PGSEL: PG1 and PG2 function select bit
This bit selects the function of the PG1 and PG2 pins.
Writing "0" to this bit makes the PG1 and PG2 pins function as subclock oscillation pins. The subclock
oscillation is enabled or disabled by the subclock oscillation enable bit (SYCC2:SOSCE).
Writing "1" to this bit makes the PG1 and PG2 pins function as general-purpose I/O ports.
bit7
Writing "0"
Writing "1"
[bit6] PFSEL: PF0 and PF1 function select bit
This bit selects the function of the PF0 and PF1 pins.
Writing "0" to this bit makes the PF0 and PF1 pins function as main clock oscillation pins. The main clock
oscillation is enabled or disabled by the main clock oscillation enable bit (SYCC2:MOSCE).
Writing "1" to this bit makes the PF0 and PF1 pins function as general-purpose I/O ports.
bit6
Writing "0"
Writing "1"
[bit5:4] Reserved bits
Always set these bits to "0".
[bit3] EC0SL: EC0 clock select bit
This bit selects the external count clock input pin (EC0) for the 8/16-bit composite timer. (Before using the
EC0 input function, enable the external count clock input of the 8/16-bit composite timer. See "CHAPTER
11 8/16-BIT COMPOSITE TIMER" for details.)
bit3
Writing "0"
Writing "1"
602
6 5
PFSEL Reserved
R/W W
1 0
Makes the PG1 and PG2 pins function as subclock oscillation pins.
Makes the PG1 and PG2 pins function as general-purpose I/O ports.
Makes the PF0 and PF1 pins function as main clock oscillation pins.
Makes the PF0 and PF1 pins function as general-purpose I/O ports.
Selects P12/EC0 pin as the external count clock input pin.
Selects P04/EC0 pin as the external count clock input pin.
FUJITSU SEMICONDUCTOR LIMITED
4 3
Reserved EC0SL
W R/W
0 0
Details
Details
Details
MB95630H Series
2 1
PPGSEL RSTOE
R/W R/W
0 1
MN702-00009-1v0-E
0
RSTEN
R/W
1