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MB95630H Series
[bit4] RDRF: Receive data register full flag bit
This flag bit shows the status of the LIN-UART receive data register (RDR).
This bit is set to "1" when received data is loaded into RDR, and cleared to "0" by reading the receive data
register (RDR).
When both the RDRF bit and the RIE bit are "1", a receive interrupt request is output.
bit4
Reading "0"
Reading "1"
[bit3] TDRE: Transmit data register empty flag bit
This flag bit shows the status of the LIN-UART transmit data register (TDR).
This bit is set to "0" by writing the transmit data to TDR, and indicates that the TDR has valid data. When
data is loaded into the transmit shift register and data transfer starts, this bit is set to "1", indicating that the
TDR does not have valid data.
When both the TDRE bit and the TIE bit are "1", a transmit interrupt request is output.
When the TDRE bit is "1", setting the LBR bit in the LIN-UART extended communication control register
(ECCR) to "1" changes the TDRE bit to "0". After the LIN synch break is generated, the TDRE bit returns to
"1".
bit3
Reading "0"
Reading "1"
Note: The initial value of the TDRE bit is "1".
[bit2] BDS: Transfer direction select bit
This bit specifies whether serial data transfer starts from the least significant bit (LSB-first, BDS = 0) or from
the most significant bit (MSB-first, BDS = 1).
bit2
Writing "0"
Writing "1"
Note: When data is written to or read from the serial data register, the data on the upper side and that on the
lower side are swapped. Therefore, if the BDS bit is modified after data is written to the RDR register,
the data in the RDR register becomes invalid. In operating mode 3 (LIN), the BDS bit is fixed at "0".
[bit1] RIE: Receive interrupt request enable bit
This bit enables or disables the receive interrupt request output to the interrupt controller.
When both the RIE bit and the receive data flag bit (RDRF) are "1", or when one or more error flag bits (PE,
ORE, FRE) is "1", a receive interrupt request is output.
bit1
Writing "0"
Writing "1"
[bit0] TIE: Transmit interrupt request enable bit
This bit enables or disables the transmit interrupt request output to the interrupt controller.
When both the TIE bit and the TDRE bit are "1", a transmit interrupt request is output.
bit0
Writing "0"
Writing "1"
MN702-00009-1v0-E
Indicates that there is no data in the receive data register (RDR).
Indicates that there is data in the receive data register (RDR).
Indicates that there is data in the transmit data register (TDR).
Indicates that there is no data in the transmit data register (TDR).
Selects LSB-first. (Serial data transfer starts from the LSB.)
Selects MSB-first. (Serial data transfer starts from the MSB.)
Disables the receive interrupt.
Enables the receive interrupt.
Disables the transmit interrupt.
Enables the transmit interrupt.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 14 LIN-UART
Details
Details
Details
Details
Details
14.7 Registers
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