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CHAPTER 3 CLOCK CONTROLLER
3.4 Clock Modes
Table 3.4-1
Clock Mode State Transition Table (2 / 2)
Current
Next State
State
Main CR clock/
(13)
Main CR PLL
clock
Sub-CR clock
(14)
Main clock
(15)
Subclock
(16)
Main CR clock/
(17)
Main CR PLL
clock
Subclock
(18)
Main clock
(19)
Sub-CR clock Same as (1) and (2)
(20)
40
When the clock mode select bits in the system clock control register (SYCC:SCS[2:0])
are set to "0b110", the device transits to main CR clock mode after waiting for the
main CR clock oscillation stabilization wait time.
When the clock mode select bits in the system clock control register (SYCC:SCS[2:0])
are set to "0b111", the device transits to main CR PLL clock mode after waiting for the
main CR PLL clock oscillation stabilization wait time.
When the clock mode select bits in the system clock control register (SYCC:SCS[2:0])
are set to "0b010", the device transits to main clock mode after waiting for the main
clock oscillation stabilization wait time.
Same as (3) and (4)
Same as (13)
Same as (14)
FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
Description
MN702-00009-1v0-E
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