Table of Contents
Advertisement
CHAPTER 4 RESET
4.1 Reset Operation
■ Overview of Reset Operation
During reset
YES
Mode fetch
Normal operation
(Run state)
In any reset, the CPU performs mode fetch after the main CR clock oscillation stabilization
wait time elapses.
■ Effect of Reset on RAM Contents
When a reset occurs, the CPU halts the operation of the command currently being executed,
and enters the reset state. However, during RAM access execution, in order to protect the RAM
access, an internal reset signal synchronized with the machine clock is generated after an RAM
access ends. This function prevents a word-data write operation from being interrupted by a
reset while data of two bytes is being written.
64
Figure 4.1-1 Reset Operation Flow
Software reset
Watchdog reset
Suppress resets
during RAM access
Sub-CR clock is ready?
NO
Sub-CR clock
oscillation stabilization
wait time reset state
FUJITSU SEMICONDUCTOR LIMITED
External reset input
Supress resets
during RAM access
Sub-CR clock is ready?
YES
NO
Sub-CR clock
oscillation stabilization
wait time reset state
Released from
external reset?
YES
Main CR clock oscillation
stabilization wait time
Capture mode data
Capture reset vector
Capture instruction code from the
address indicated by the reset
vector and execute the instruction.
MB95630H Series
Power-on reset/
low-voltage delection
reset
Sub-CR clock
oscillation stabilization
wait time reset state
NO
MN702-00009-1v0-E
Advertisement
Table of Contents
